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    • 专利摘要:
    The invention relates to a method of manufacturing an integrated circuit (1), comprising the steps of: -providing a substrate (100), the substrate being provided with first and second dummy grids and an encapsulation layer (106); ); removing the first and second dummy gates to provide first and second grooves (23,33) in said encapsulation layer (106); simultaneously depositing a layer of gate insulator (107) at least in the bottom of the first groove and on a side wall of the second groove; -forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell from and other of said gate insulator layer deposited on a side wall of the second groove.
    公开号:FR3034906A1
    申请号:FR1553070
    申请日:2015-04-09
    公开日:2016-10-14
    发明作者:Laurent Grenouillet；Yves Morand；Maud Vinet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The invention relates to OxRAM memories, and in particular cointegration of such memories with field effect transistors. In order to overcome the limitations in terms of miniaturization, power consumption and manufacturing complexity of non-volatile floating gate memory technologies, the semiconductor industry is developing different alternative technologies. Among alternative nonvolatile memory technologies under development, RRAM type memories are of technical interest. The RRAM type memories are based on the formation and reversible breaking of a conductive filament: a dielectric material, which is normally insulating, may be forced to be conductive through a filament or conduction path after the application of the conductive filament. a sufficiently high voltage. Once the filament is formed, it can be reset or programmed by an appropriately applied voltage. In the particular case of OxRAM memories, the conductive filament is made from oxygen vacancies in an insulating material based on metal oxide. OXRAM memories have a very good thermal stability, theoretically allowing to store information reliably for several years at high temperature. An OxRAM memory cell can be produced from a base memory point according to three known solutions. In a first, simplest approach, the memory point can be used as a basic memory cell, and used in a configuration in which parallel bit lines are traversed by perpendicular word lines, with the switching material. placed between the word line and the bit line at each crossing point. This configuration is called a cross point cell. Since this architecture may lead to a large parasitic current flowing through unselected memory cells from neighboring cells, the crosspoint matrix may have very slow read access. In a second approach, a selection element may be added to eliminate this parasitic current, but this selection element induces electrical over-consumption. In a third approach, a field effect transistor is added, facilitating the selection of a memory point and thus optimizing the access time, while limiting the current flowing in the cell, thus avoiding transient overcurrents that can alter or even destroy the cell. In this third approach, however, the integration density is strongly altered, the selection transistors occupying a significant area of the integrated circuit substrate. The document `Higlhy scalable Non-volatable Resistive Memory using 5 Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses' by IG Baek et alias, published by the IEEE in 2004, describes an example of cointegration of OxRAM memory cells with selection transistors . In order to improve the integration density of the integrated circuit, this document proposes to integrate the selection transistors in a pre-metallization layer or FEOL layer, and to integrate the OXRAM memory points in a layer according to metallization or BEOL layer, in line with the selection transistors. In practice, such cointegration does not make it possible to increase the integration density as much as desired, while at the same time implying a considerably increased complexity of the manufacturing process. The invention aims to solve one or more of these disadvantages. The invention thus relates to a method for manufacturing an integrated circuit including at least one field-effect transistor and an OxRam-type memory cell, comprising the steps of: providing a substrate including a semiconductor layer; substrate 20 being provided with first and second dummy gates and an encapsulation layer in which said dummy gates are disposed, at least the first dummy gate being formed on the semiconductor layer of the substrate; removing the first and second dummy gates to provide first and second grooves in said encapsulation layer; simultaneously depositing a layer of gate insulator at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode of said transistor in the first groove above said gate insulator layer, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said gate insulator layer deposited on a side wall of the second groove. According to a variant, the method comprises forming an insulating wall 35 disposed between said first and second electrodes of the memory cell, this insulating wall including said gate insulator layer deposited on a side wall of the second groove, and having a thickness sized to selectively form a conductive filament upon application of a potential difference between the first and second electrodes. According to a further variant, the method further comprises forming an additional layer of insulator in said second groove on said gate insulator layer, said additional layer of insulator being included in said insulating wall disposed between said insulating layer first and second electrodes.
    [0002] In another variant, said deposited gate insulator layer includes a material selected from the group consisting of HfO2, HfSiON, HfA10, TiOx, Al2O3 or NiO. According to yet another variant, the formation of the source, drain and said first electrode electrodes of the memory cell includes the formation of additional grooves in the encapsulation layer, on either side of the first groove and on the side of the second gorge. According to a variant, the method comprises depositing a protective layer in the first and second grooves respectively on said gate electrode and said second electrode of the memory cell, said protective layer being formed in a material different from the layer encapsulation, the formation of said additional grooves including self-aligned etching of the encapsulation layer on either side of the protective layer. According to another variant, the formation of the source, drain and said first electrode electrodes of the memory cell includes: the formation of a titanium layer on the walls of said additional grooves; the formation of a layer of titanium nitride on the titanium layer; depositing a metal layer on said titanium layer. According to another variant, said first electrode formed for said memory cell also forms one of said source or drain electrodes formed for said transistor. According to another variant, said supplied substrate comprises an isolation trench and the second dummy gate is formed on said isolation trench. According to yet another variant, said substrate is of silicon-on-insulator type. Alternatively, the method comprises connecting said first and second electrodes of said memory cell to an electronic circuit configured to selectively apply a potential difference between the first and second conductive filament inducing electrodes through said gate insulator layer. deposited on a side wall of the second groove. According to another variant, the method comprises: the formation of said encapsulation layer; - prior to the formation of said encapsulation layer, a full-plate deposit of an insulating layer covering the first and second dummy grids; masking said insulating layer at the first dummy gate and removing said insulating layer above and on either side of the second dummy gate; preserving a portion of said insulating layer on either side of said formed gate electrode so as to form spacers for said gate electrode.
    [0003] According to another variant, said masking and said withdrawal are performed prior to said formation of said encapsulation layer. According to yet another variant, said masking and said withdrawal are made subsequent to the formation of said additional grooves. The invention also relates to an integrated circuit including: a field effect transistor; a memory cell of the OxRAM type; Wherein: the field effect transistor and the memory cell are included in a pre-metallization layer and wherein a gate insulator layer of the field effect transistor and an insulation layer selectively forming a filament memory cell drivers include the same material. Other characteristics and advantages of the invention will emerge clearly from the description which is given hereinafter, by way of indication and in no way limiting, with reference to the appended drawings, in which: FIGS. 1 to 24 are views in transverse section during different steps of a first embodiment of a method of manufacturing an integrated circuit according to the invention; FIG. 25 is a cross-sectional view of an integrated circuit variant according to the invention; FIG. 26 illustrates a schematic sectional view of different successive materials used in an OxRAM cell according to the invention; FIGS. 27 to 48 are cross-sectional views during different stages of a second embodiment of a method of manufacturing an integrated circuit according to the invention; FIGS. 49 and 50 schematically illustrate top views of different integrated circuit configurations according to the invention; FIG. 51 schematically illustrates a sectional view of an integrated circuit variant according to the invention; FIGS. 52 to 54 schematically illustrate top views of other integrated circuit configurations according to the invention. The invention proposes cointegrating OxRAM memory cells and their selection transistors in the same pre-metallization layer, from the same materials, formed during common deposition steps. Fig. 1 is a cross-sectional view of an integrated circuit 1 at the beginning of a manufacturing method according to a first embodiment of the invention. At the beginning of this manufacturing method, a semiconductor substrate 100 is provided, typically a P-type residual doping silicon semiconductor substrate. In the example illustrated, the substrate 100 is of massive type (bulk in English language). Insulation trenches 22 and 32 are formed in the substrate 100. The isolation trenches 22 and 32 may have a depth known per se. The isolation trenches 22 and 32 may be made in a manner known per se from a material such as silicon oxide. The semiconductor substrate 100 is covered with an etch stop layer 101. The etch stop layer 101 is here formed of an electrical insulating material. The etch stop layer 101 is for example made of the same material as the isolation trenches 22 and 32, for example silicon oxide. For example, the etch stop layer 101 has a thickness of between 2 and 6 nm. A dummy gate 21 of a transistor 2 is disposed on the barrier layer 101 between the isolation trenches 22 and 32.
    [0004] The dummy gate 21 may advantageously have a thickness of between 50 and 150 nm, and preferably of the order of 100 nm. The dummy gate 21 here comprises a semiconductor element 212 formed on the barrier layer 101. The semiconductor element 212 may be formed of silicon. The semiconductor element 212 may be formed of the same material as the substrate 100 or the same material with a different crystallographic structure. The semiconductor element 212 may also be formed of polysilicon. The semiconductor element 212 is for example made with a thickness of between 30 and 90 nm, and advantageously of 70 nm. The dummy gate 21 here comprises an insulating element 211, formed on the semiconductor element 212. The insulating element 211 is typically made of a masking material, for example silicon nitride. The insulating element 211 is for example made with a thickness of between 20 and 60 nm, and advantageously of 30 nm. A dummy gate 31 of a memory point 3 is here advantageously disposed on the isolation trench 32. The dummy gate 31 here comprises a semiconductor element 312 formed on the isolation trench 32. Conductor 312 is for example formed in the same material as semiconductor element 212 and may have the same thickness as semiconductor element 212. Dummy gate 31 here comprises an insulating element 311, formed on the element semiconductor 312. The insulating element 311 is typically made of the same material as the insulating element 211 and may have the same thickness as the insulating element 211. The use of dummy grids is used in so-called grid processes. last (gate last in English language). The dummy gates 21 and 31 may have a defined geometry in a manner known per se by prior steps of photolithography and selective etching. The barrier layer 101 and the isolation trenches 22 and 32 make it possible, for example, to produce etchings delimiting the dummy gates 21 and 31, without etching in the semiconductor substrate 100. The insulation thicknesses 211 and 311 can For example, they may be deposited beforehand by a PECVD deposit (plasma-enhanced chemical vapor deposition). At the stage illustrated in FIG. 2, a layer 102 of insulating material is deposited so as to form spacers on either side of the dummy grids 21 and 31. The layer 102 is for example deposited full plate, for example by a ALD (atomic layer deposition) process. The layer 102 may be made of a material such as silicon nitride, or of lowK type materials such as SiCBN or SiOCN. The thickness of the spacers formed on either side of the dummy gates 21 and 31 is for example between 4 and 8 nm, typically 6 nm. At the stage illustrated in FIG. 3, a masking 103 has been defined to cover the dummy gate 31 and a part of the layer 102 on either side of the dummy gate 31. The masking 103 has been removed by photolithography between the FIG. isolating trenches 22 and 32, and has been removed from the dummy gate 21. The masking 103 has thus been retained only on the areas of memory points 3. By etching, the layer 102 of part and other of the dummy gate 21, advantageously by an anisotropic etching thus making it possible to form spacers. By etching, the stop layer 101 is also removed from each other of the dummy gate 21, for example by etching. The semiconductor of the substrate 100 is thus discovered on either side of the dummy gate 21. At the end of these etches, a portion 213 of the barrier layer is preserved under the element 212 and spacers 214 are retained. on both sides of the elements 211 and 212 of the dummy gate 21.
    [0005] At the stage illustrated in FIG. 4, the masking 103 is removed in a manner known per se, so as to discover the layer 102 remaining in the area of the memory point 3. Semiconductor elements 222 and 221 advantageously consist of either side of the dummy gate 21, on the semiconductor of the substrate 100, between the isolation trenches 22 and 32. The semiconductor elements 222 and 221 are typically formed to a thickness advantageously between 10 nm and 30 nm. The semiconductor elements 222 and 221 are typically epitaxially formed on the semiconductor of the substrate 100. The elements 222 and 221 are typically obtained by selective epitaxial growth of silicon on crystalline silicon of the substrate 100. They can also be obtained by selective growth of SiGe. The elements 221 and 222 may be doped by a subsequent implantation step, not detailed herein, or by in-situ doping during the epitaxial step. Prior to the epitaxial step, a recess (recess in English) is advantageously provided in the material of the substrate 100, for example to put the channel under stress of a solid substrate 100. In the stage illustrated in FIG. a barrier layer 104 has been deposited to cover the area of the transistor 2. The barrier layer 104 covers in particular the area between the isolation trenches 22 and 32 and the dummy gate 21. The barrier layer 104 is for example formed by a full-plate deposit of an insulator so as to cover the dummy gate 31. The barrier layer 104 is for example formed by a nitride deposit (for example CESL type for contact Etch 25 Stop Layer in language English). The barrier layer 104 is for example deposited to a thickness of about 6 nm. At the stage illustrated in FIG. 6, a masking 105 has been defined to cover the dummy gate 21 and the layer 104 between the isolation trenches 22 and 32. The masking 105 has been obtained by photolithography to discover the zones of the memory points 3. The masking 105 has thus been retained only on the transistor zones 2. In the stage illustrated in FIG. 7, the layers 102 and 104 on either side of the dummy gate 31 have been removed by etching. for example by an isotropic etching. The isolation trench 32 is thus discovered on either side of the dummy gate 31. The spacers are removed on either side of the dummy gate 31, simultaneously when using an isotropic etching.
    [0006] At the stage illustrated in FIG. 8, the masking 105 is removed in a manner known per se, so as to discover the stop layer 104 remaining in the region of the transistor 2.
    [0007] At the stage illustrated in FIG. 9, an encapsulation of the integrated circuit 1 in an insulating layer 106 is carried out. The encapsulation is typically made full plate by means of a silicon oxide. A chemical mechanical polishing was then performed and was interrupted after reaching the elements 211 and 311. These elements 211 and 311 act as a barrier layer 10 for chemical mechanical polishing. In the stage illustrated in FIG. 10, the elements 211 and 311 are removed until the semiconductor elements 212 and 312 are respectively reached. Grooves 23 and 33 are thus formed in the insulating layer 106. removal of the silicon nitride to reach the elements 212 and 312 is for example carried out by wet etching with hot H3PO4 (for example between 150 and 160 ° C). Such etching is particularly selective with respect to the silicon of the elements 212 and 312 and to the silicon oxide of the layer 106 for example.
    [0008] In the stage illustrated in FIG. 11, the elements 212 and 312 have been removed. The grooves 23 and 33 then reach respectively the stop layer portion 213 and the deep insulation trench 32. The removal of the elements 212 and 312 may for example be achieved by chemical etching with TMAH (Tetramethylammonium hydroxide) or NH4OH. In the stage illustrated in FIG. 12, the stop layer portion 213 is removed. The groove 23 then reaches the substrate 100. This shrinkage is for example carried out by chemical etching with hydrofluoric acid. Such chemical etching further makes it possible to prepare the surface of the substrate 100 for a subsequent deposition step. A superficial portion of the deep isolation trench 32 is also etched. At the stage illustrated in FIG. 13, an insulation layer 107 has been formed covering the region of the transistor 2 and the area of the memory point 3. The insulating layer 107 covers here the upper face of the layer 106, the flanks of the grooves 23 and 33, and respectively the substrate 100 and the isolation trench 32 at the bottom of the grooves 23 and 33. The grooves 23 and 33 are not completely filled by the insulating layer 107. Insulating layer 107 is formed here by a full-plate deposit. The insulating layer 107 may for example be deposited by a method of the ALD type, which makes it possible to obtain a homogeneous thickness on the vertical faces and the horizontal faces. The material chosen for the insulator layer 107 is a material compatible both to form a gate insulator for the transistor 2 and to form the insulator of the conductive filament of the memory point 3. The material of the insulator layer 107 may for example be of the Hk or High-K type (a High-K material usually designates a material whose relative dielectric constant is at least equal to 6). The material of the insulating layer 107 may for example be HfO 2, a common material for producing a gate insulator. Other materials may be used for the insulating layer 107, among which, without limitation, the HfSiON or the HfAIO (favorable to the performance of the memory point 3). For HfO 2, it is possible, for example, to envisage a thickness of 10 nm of the insulating layer 107 for a potential difference of 3V, or a thickness of 3 nm for a potential difference of at most 1V. The layer 107 will have a suitable thickness and material, in a manner known per se, to allow the formation of a conductive filament of an OxRAM memory cell. The thickness of the layer 107 deposited on the substrate 100 characterizes the thickness of the gate insulator of the transistor 2. The thickness of the layer 107 deposited on the flanks of the groove 33 characterizes the thickness of the conductive filament. the OxRAM memory cell. A layer 107 made of HfO 2 will preferably have a thickness of between 1 and 10 nm (and preferably between 3 and 5 nm).
    [0009] FIG. 14 illustrates an alternative manufacturing method in which the thickness of the insulator layer 107 formed is greater than the level of the memory point 3 with respect to the transistor 2. The method of forming the insulating layer 107 according to this variant may comprise a first deposition step 30 full plate of insulating material with a first thickness t1. In a second step, the area of the memory point 3 is masked and the insulation deposit is removed by etching in the region of the transistor 2. After removal of the masking of the memory point 3, the memory point 3 remains covered by a layer insulation of a thickness t1. In a third step, a deposit of insulating material is made full plate with a thickness t2. The insulator layer 107 formed then has a thickness t2 at the level of the transistor 2, and a thickness t1 + t2 at the memory point 3. The thickness of the insulating layer 107 is defined in the different zones by steps full plate deposit, it can easily be obtained industrially with great precision.
    [0010] This variant illustrates the possibility of having different thicknesses of the layer 107 for the transistor 2 or the memory point 3, according to their respective dimensioning constraints. It is of course also possible to envisage that the thickness of the layer 107 for the transistor 2 is greater than that of the memory point 3. FIG. 15 illustrates the continuation of the manufacturing method corresponding to the variant of FIG. in FIG. 15, a conductive material layer 109 has been formed on the layer 107. The layer of conductive material 109 formed covers the region of the transistor 2 and the area of the memory point 3. The layer of material conductor 109 covers here the upper face of the layer 107 and the flanks of the grooves 23 and 33, as well as the bottom of the grooves 23 and 33. The grooves 23 and 33 are not completely filled by the layer 109.
    [0011] The layer of conductive material 109 is here formed by a full-plate deposit. The layer of conductive material 109 may for example be deposited by a PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) process. Such deposition methods typically make it possible to form a layer 109 whose thickness on the horizontal faces is greater than that of the vertical faces. The thickness of the deposition of the layer 109 on the side faces of the grooves 23 and 33 is for example typically between 3 and 10 nm, and preferably between 3 and 6 nm, in particular to promote the operation of the memory point 3. On can also consider an ALD depot for layer 109.
    [0012] The material chosen for layer 109 may for example be TiN or TaN. This material is for example chosen to have an appropriate output work for the gate of transistor 2, and to form an electrode of an OxRam memory point 3.
    [0013] FIG. 16 illustrates the continuation of the manufacturing method corresponding to the variant of FIG. 14. The conductive material layer 109 is here formed on an insulating layer 107 having distinct thicknesses at the level of the transistor 2 and the memory point 3 .
    [0014] Independently of the method of forming the insulator layer 107, the thickness of the conductive material layer 109 formed may be different at the transistor 2 and the memory point 3. For example, to obtain a thickness of the layer 109 at the level of the memory point 3 greater than its thickness at the level of the transistor 2, it is possible to perform a first step of depositing a full plate of conductive material with a thickness (thickness on the vertical faces) t3. In a second step, the area of the memory point 3 is masked and the deposition of conductive material is etched in the region of the transistor 2. After removal of the masking of the memory point 3, the memory point 3 remains covered by a layer of conductive material with a thickness t3. In a fourth step, a deposit of the conductive material is made full plate with a thickness t4 (thickness on the vertical faces). The layer of conductive material 109 formed then has a thickness t3 at the level of the transistor 2, and a thickness t3 + t4 at the memory point 3.
    [0015] Since the thickness of the conductive material layer 109 is defined in the different zones by full-plate deposition steps, it can easily be obtained industrially with great precision. The thickness of the conductive material layer 109 is advantageously between 2 and 20 nm.
    [0016] FIG. 17 illustrates the continuation of the manufacturing method corresponding to the variant of FIG. 15. In the stage illustrated in FIG. 17, metal was deposited on the layer 109, so as to fill the grooves 23 and 33 by metal studs 24 and 34 respectively. The deposited metal to form the pads 24 and 34 is typically Tungsten. It is also possible in a nonlimiting manner to form the pads with copper, cobalt or WSi. A chemical mechanical polishing was then carried out and was interrupted after having discovered the layer 106, which then serves as a stop layer for chemical mechanical polishing.
    [0017] At the stage illustrated in FIG. 18, grooves 25 and 35 are formed in the layer 106. The grooves 25 and 35 are respectively formed by removal of the upper part of the studs 24 and 34 and withdrawal of the upper part. layers 107 and 109. These recesses are typically made by a plasma etching (RIE) etching (RIE for Reactive Ion Etching, or ICP for Inductively Coupled Plasma in English). In the case where the trenches 24 and 34 are W, etching based on the following gases: BCI3, C12, SF6, Ar, N2H2, 02 can be envisaged. These withdrawals are interrupted for example at the expiration of a time delay, so as to form grooves 25 and 35 deep enough to form sufficiently thick plugs at a later stage. The layer 104 is here found at the bottom of the groove 25. In the stage illustrated in FIG. 19, the plugs 26 and 36 have been formed filling the grooves 25 and 35, respectively. The plugs 26 and 36 are typically formed by deposition of an insulating material, for example silicon nitride. The formation of the plugs was here followed by a chemical mechanical polishing step until the upper surface of the layer 106 (which serves as a stop layer for chemical mechanical polishing) is discovered. The plugs 26 and 36 formed serve for subsequent protection of the materials they cover, in particular the gate stack of the transistor 2 and the insulator and an electrode of the memory point 3. In the stage illustrated in FIG. photolithography has been carried out to define contact zones on either side of the plugs 26 and 36. Thus, only parts of the layer 106 in line with the isolation trenches 22 and 32 are masked. A step of etching the unmasked areas of the layer 106 is then carried out, until the layer 104 and the isolation trench 32 are discovered on either side of the plugs 26 and 36. Grooves 28 and 29 are thus formed on both sides of the plug 26 and grooves 38 and 39 15 are formed on either side of the plug 36. The etching step is typically performed selectively with respect to the material of the plugs 26 and 36 (For example by an oxide etching) or carried out anisotropically, so that the etched areas on either side of the plugs 26 and 36 are self-aligned. Such self-alignment (the contacts obtained are usually designated SAC for Self Aligned Contacts in English) makes it possible to guarantee optimum compactness of the integrated circuit 1 formed, without being limited by lithography dimensions. In the stage illustrated in FIG. 21, the layer 104 has been removed on either side of the plug 26, until the semiconductor elements 222 and 221 are discovered. The removal of the layer 104 is for example carried out by an etching anisotropic. In the stage illustrated in FIG. 22, silicidation of the semiconductor elements 221 and 222 on either side of the plug 26 has advantageously been performed. The silicidation typically comprises a Ni or NiPt type metal deposition, for example, annealing, then chemical removal of the unreacted metal, and generally a new annealing step. Silicone semiconductor elements 223 and 224 are thus formed on either side of the plug 226. The silicidation can be carried out so as to form elements 223 and 224 of NiSi or NiPtSi, for example. Advantageously, the silicidation is carried out on a thickness of 5 to 15 nm. At the stage illustrated in FIG. 23, a metal layer 110 was deposited on the silicide elements 223 and 224, and on the insulation trench 32, as well as on the sides of the grooves 28, 29 and 30. 38,39 respectively formed on either side of the plugs 26 and 36. The deposited metal is typically titanium. Titanium promotes a good fixation on the surfaces on which it is deposited. The thickness of metal deposited on the flanks of the grooves 5 can advantageously be between 2 and 15 nm. The thickness of metal deposited on the bottom of the grooves may advantageously be between 2 and 15 nm. The metal layer 110 is advantageously deposited by a compliant process (of the ALD or CVD type). Subsequently, a conductive metal alloy layer 111 was deposited on the metal layer 110. The metal alloy layer 111 typically includes TiN. The thickness of the layer 111 deposited on the flanks of the grooves may advantageously be between 3 and 10 nm. The thickness of the layer 111 deposited on the bottom of the grooves may advantageously be between 3 and 10 nm. The layer 111 is advantageously deposited by a compliant process (ALD, or CVD). Metal was then deposited on the layer 111, so as to fill the grooves by metal studs 274 and 275 on either side of the plug 26, and metal studs 374 and 375 on either side of the plug. cap 36. The metal deposited to form the pads is typically Tungsten. It is also possible to envisage, without limitation, aluminum, cobalt, copper, platinum or WSi. A chemical mechanical polishing was here then carried out and was interrupted after reaching the plugs 26 and 36. The presence of a possible layer of TiN between the metal layer 110 and tungsten pads acts as a tie layer for tungsten and fluorine diffusion barrier, frequently used as a precursor gas during tungsten deposition. In the stage illustrated in FIG. 24, interconnecting metal contacts 273, 373, 272, 271, 372, 371 were respectively formed with the pads 24, 34, 274, 275, 374, 375. The metal contacts 272, 271 and 273 are respectively in contact with the source, the drain and the gate of the transistor 2. In practice, the memory point 3 comprises a first memory cell between the pad 34 and the pad 374 on the one hand and another memory cell between the pads 34 and the pads 375.
    [0018] By having a stud 275 of the transistor 2 dissociated from the pin 374 of the memory point 3, it is possible to dissociate their operation and possibly to prevent the operation of one from degrading the operation of the other.
    [0019] FIG. 26 is a diagrammatic sectional view along a plane parallel to the substrate 100, illustrating the succession of layers used for the formation of an OxRAM cell of the memory point 3.
    [0020] By forming the memory point 3 in the pre-metallization layer, it is possible to benefit from a very small pitch (pitch in English) available for such a pre-metallization layer, in order to reduce the surface area of the substrate 100 covered by the memory point 3. A 90nm or 64nm step may for example be used.
    [0021] The process is based on a last grid formation, which makes it possible to form an insulation deposit on a sidewall of a trench, and thus to produce an insulating layer for a horizontal conductive filament. In a manufacturing method according to the invention, a very large number of steps and materials are common for the formation of the transistor 2 and the formation of the memory point 3. Thus, the manufacturing method is substantially simplified and its cost of returns is particularly reduced. In the illustrated method, the memory point 3 is advantageously (but not necessarily) formed on an isolation trench in order to take advantage of an integrated circuit portion needed to isolate components from each other but usually not widely used in a layer of insulation. before metallization. The integration density of the integrated circuit 1 can thus be further increased. Figure 25 illustrates an integrated circuit variant 1 obtainable by a similar manufacturing process. This variant aims to increase the integration density of integrated circuit 1 by using common electrodes for selection transistors 2 and 4 and two memory cells of memory point 3. Transistor 2 of FIG. 25 has substantially the same structure as The transistor 4 has substantially the same structure as the transistor 2. The transistor 4 is formed between an isolation trench 42 and the isolation trench 32. The transistor 4 comprises a metal stud of gate 44, a metal drain pad 474 and a source metal pad 475. The pads 44, 474 and 475 are connected to metal contacts 473, 472 and 471, respectively. The metal contacts 471, 472 35 and 473 are respectively in contact with the source, the drain and the gate of the transistor 4. A first cell of the memory point 3 shares a common electrode with the transistor 2, by the pad 275. A second cell of the memory point 3 shares a common electrode with the transistor 4, by the pad 474.
    [0022] Figure 27 is a cross-sectional view of an integrated circuit 1 at the beginning of a manufacturing method according to a second embodiment of the invention. At the beginning of this manufacturing process, a semiconductor substrate 100, identical to that of FIG. 1, is provided. Insulating trenches 22 and 32 identical to that of FIG. 1 are formed in the substrate 100. Dummy 21 (dummy gate in English) of a transistor 2 is disposed on the substrate 100, between the isolation trenches 22 and 32. The dummy gate 21 here comprises an insulating portion 213, a semi-conductor element 212 formed on the insulating part 213, and an insulating element 211 formed on the semiconductor element 212. The insulating part 213 may be made of the same material as the insulating trenches 22 and 32. The insulating part 213 may for example have a thickness of between 2 and 6 nm. The semiconductor element 212 and the insulating element 211 may have the same materials and the same thickness as in the example of FIG. 1. A dummy gate 31 of a memory point 3 is here advantageously disposed on the trench of the trench. The dummy gate 31 here comprises a semiconductor element 312 formed on the isolation trench 32. The dummy gate 31 may be identical to that described with reference to FIG.
    [0023] At the stage illustrated in FIG. 28, a layer of insulating material has been deposited so as to form spacers 214 and 313 on either side of the dummy gates 21 and 31, respectively. This material may be a material such as silicon nitride, or a lowK type material such as SiCBN or SiOCN. The thickness of the spacers 214 and 313 formed on either side of the dummy gates 21 and 31 is, for example, between 5 and 7 nm, typically 6 nm. The deposition of the insulating material of the spacers 214 and 313 can be made full plate by by an ALD method, followed by an etching step (eg anisotropic etching) so as to remove this insulating material from the respective upper surfaces of the substrate 100 and the isolation trenches 22 and 32. At the stage illustrated in FIG. 29, semiconductor elements 222 and 221 are advantageously formed on either side of the dummy gate 21, on the semiconductor of the substrate 100, between the isolation trenches 22 and 32. The semiconductor elements 222 and 221 are typically formed to a thickness of 10 to 35 nm. The semiconductor elements 222 and 221 are typically epitaxially formed on the semiconductor of the substrate 100. The elements 222 and 221 are typically obtained by selectively epitaxial growth of silicon on crystalline silicon of the substrate 100. They can also be obtained by selective growth of SiGe. The elements 221 and 222 may be doped by a subsequent implantation step, not detailed here, or by in-situ doping during the epitaxial step. Prior to the epitaxial step, a recess is advantageously provided in the material of the substrate 100, for example to put the channel under stress of a solid substrate 100.
    [0024] In the stage illustrated in FIG. 30, a layer 104 of insulating material is deposited in such a way as to increase the thickness of the spacers on either side of the dummy gates 21 and 31. The layer 104 is for example deposited full plate, by example by an ALD (atomic layer deposition) method. The layer 104 may be made of a material such as silicon nitride, or of lowK type materials such as SiCBN or SiOCN. The total thickness of the spacers obtained after deposition of the layer 104 is advantageously between 5 and 15 nm. In the stage illustrated in FIG. 31, encapsulation of the integrated circuit 1 in an insulating layer 106 has been achieved. The encapsulation is typically carried out full plate by means of a silicon oxide. A chemical mechanical polishing was then carried out and was stopped after reaching layer 104.
    [0025] In the stage illustrated in FIG. 32, grooves 23 and 33 are formed in the insulating layer 106, by removing the elements 211 and 311, the upper part of the layer 104 and a part of the spacers 214 and 313 until reaching the semiconductor elements 212 and 312, respectively. Silicon nitride removal to the elements 212 and 312 is, for example, achieved by wet etching with hot H 3 PO 4 (by example between 150 and 160 ° C). In the particular case of elements 212 and 312 made of silicon and a layer 106 made of silicon oxide, such an etching proves to be particularly selective.
    [0026] In the stage illustrated in FIG. 33, the elements 212 and 312 have been removed. The grooves 23 and 33 then reach respectively the stop layer portion 213 and the deep insulation trench 32. The removal of the elements 212 and 312 may for example be achieved by chemical etching with TMAH (Tetramethylammonium hydroxide) or NH4OH.
    [0027] To achieve the configuration shown in Figure 33, the removal of the insulating portion 213. The groove 23 then reaches the substrate 100. This removal is for example carried out by chemical etching hydrofluoric acid. Such chemical etching also makes it possible to prepare the surface 5 of the substrate 100 for a subsequent deposition step. In the stage illustrated in FIG. 34, an insulation layer 107 has been formed covering the region of the transistor 2 and the zone of the memory point 3. The insulating layer 107 covers here the upper face of the layer. 106, the flanks of the grooves 23 and 33, and respectively the substrate 100 and the isolation trench 32 at the bottom of the grooves 23 and 33. The grooves 23 and 33 are not completely filled by the insulating layer 107. insulation layer 107 is here formed by a full-plate deposit. The insulating layer 107 may for example be deposited by a method of the ALD type, which makes it possible to obtain a homogeneous thickness on vertical faces and horizontal faces during the same deposition step. The material chosen for the insulator layer 107 may be identical to that described for the method of the first embodiment, compatible both for forming a gate insulator for the transistor 2 and for forming the conductive filament insulation of the memory point 3. The layer 107 will have a thickness and a suitable material, in a manner known per se, to allow the formation of a conductive filament of an OxRAM memory cell. The thickness of the layer 107 deposited on the substrate 100 characterizes the thickness of the gate insulator of the transistor 2. The thickness of the layer 107 deposited on the flanks of the groove 33 characterizes the thickness of the conductive filament. the OxRAM memory cell. A layer 107 made of HfO 2 will preferably have a thickness of between 1 and 10 nm (and preferably between 3 and 5 nm).
    [0028] Figure 34 illustrates an alternative manufacturing method in which the thickness of the insulator layer 107 formed is greater than the level of the memory point 3 with respect to the transistor 2. The method of forming the insulating layer 107 according to this variant may comprise a first full-plate deposition step of insulating material with a first thickness t1. In a second step, the area of the memory point 3 is masked and the insulation deposit is removed by etching in the region of the transistor 2. After removal of the masking of the memory point 3, the memory point 3 remains covered by a insulation layer with a thickness t1. In a third step, a deposit of insulating material is made full plate with a thickness t2. The insulating layer 107 formed then has a thickness t2 at the level of the transistor 2, and a thickness t1 + t2 at the memory point 3. The thickness of the insulating layer 107 is defined in the different zones by full plate deposition steps, it can easily be obtained industrially with great precision.
    [0029] This variant illustrates the possibility of having different thicknesses of the layer 107 for the transistor 2 or the memory point 3, according to their respective dimensioning constraints. It is of course also possible to envisage that the thickness of the layer 107 for the transistor 2 is greater than that of the memory point 3.
    [0030] FIG. 35 illustrates a variant of the manufacturing method in which the thickness of the insulator layer 107 formed is homogeneous at the memory point 3 and at the level of the transistor 2.
    [0031] FIG. 36 illustrates the continuation of the manufacturing method corresponding to the variant of FIG. 35. In the stage illustrated in FIG. 36, a layer of conductive material 109 was formed on the layer 107. Conductive material 109 formed covers the region of transistor 2 and the area of memory point 3. Conductive material layer 109 here covers the upper surface of layer 107 and the flanks of grooves 23 and 33, as well as the bottom of grooves 23 and 33. The grooves 23 and 33 are not completely filled by the layer 109. The layer of conductive material 109 is here formed by a full-plate deposit. The layer of conductive material 109 may for example be deposited by a PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) or ALD method. The material and / or the thickness of the layer 109 may be identical to those of the method according to the first embodiment.
    [0032] In the stage illustrated in FIG. 37, metal was deposited on the layer 109, so as to fill the grooves 23 and 33 by metal studs 24 and 34 respectively. The deposited metal to form the pads 24 and 34 may be identical to that described for the method according to the first embodiment. A chemical mechanical polishing was then performed and was interrupted after having discovered layer 106. In the stage illustrated in FIG. 38, grooves 25 and 35 were formed in layer 106. Grooves 25 and 35 are respectively formed by removal of the upper portion of the studs 24 and 34 and removal of the upper portion of the layers 107 and 109. These recesses are typically made by a plasma etching type of etching (RIE for Reactive Ion Etching, or ICP for Inductively Coupled Plasma in English). In the case where the trenches 24 and 34 are W, etchings based on the following gases: BCI3, C12, 02 can be envisaged. These withdrawals are interrupted for example at the expiration of a time delay, so as to form grooves 25 and 35 deep enough to form sufficiently thick plugs at a later stage. The layer 104 is then discovered at the bottom of the groove 25.
    [0033] In the stage illustrated in FIG. 39, plugs 26 and 36 were formed filling the grooves 25 and 35 respectively. The plugs 26 and 36 are typically formed by deposition of an insulating material, for example silicon nitride. The formation of the plugs has here been followed by a chemical mechanical polishing step until the upper surface of the layer 106 is discovered. The plugs 26 and 36 formed serve for subsequent protection of the materials which they cover, in particular the gate stack of transistor 2 and the insulator and an electrode of memory point 3. In the step illustrated in FIG. 40, photolithography has been carried out to define contact zones on either side of plugs 26 and 36. Thus, only parts of the layer 106 in line with the isolation trenches 22 and 32 are masked. A step of etching of the unmasked areas of the layer 106 is then carried out, until the layer 104 is discovered on either side of the plugs 26 and 36. Grooves 28 and 29 are thus formed on the other hand and on the other side. Other of the plug 26 and grooves 38 and 39 are formed on either side of the plug 36. The etching step is typically performed selectively with respect to the material of the plugs 26 and 36 (for example by means of an etching). oxide), so that the etched areas on either side of the plugs 26 and 36 are self-aligned.
    [0034] In the stage illustrated in FIG. 41, a masking 105 has been defined to cover the dummy gate 21 and the layer 104 between the isolation trenches 22 and 32. The masking 105 fills in particular the isolation trenches 28 and 29. masking 105 was removed by photolithography to discover the zones of the memory points 3. The masking 105 has thus been retained only on the transistor zones 2. In the stage illustrated in FIG. 42, the layer 104 has been removed from the and other of the dummy gate 31 and the cap 36 by etching, for example by anisotropic etching. The isolation trench 32 is thus discovered on either side of the dummy gate 31. The spacers are removed on either side of the dummy gate and the plug 36.
    [0035] At the stage shown in FIG. 43, the masking 105 is removed in a manner known per se, so as to discover the stop layer 104 remaining in the zone of the transistor 2. According to a variant not illustrated, following the illustrated stage. in FIG. 40, it is possible to deposit a full-plate insulator, for example silicon oxide, and for example by a method of the ALD type. By photolithography, it is possible to mask the zone of the transistor 2 and to discover the zone of the memory point 3. It is then possible to etch this insulating deposit in the zone of the memory point 3 until it reaches the layer 104. the deposited insulating layer 15 is a silicon oxide, the etching may be of reactive ionic etching type. Masking of the zone of transistor 2 can be removed afterwards. Then, the layer 104 can be removed on either side of the dummy gate 31 and the plug 36 by etching, for example by etching with orthophosphoric acid. The isolation trench 32 is thus discovered on both sides of the dummy gate 31 and the plug 36. The spacers are removed on either side of the dummy gate and the plug 36. This step of withdrawal by etching may also be carried out with an HFEG-type mixture (HF = hydrofluoric acid, EG = Ethylene Glycol), in order to remove both the layer 104 as described above, and also remove some of the previously deposited silicon oxide in the zone of the transistor 2. In the stage illustrated in FIG. 44, the layer 104 is removed on either side of the plug 26, until the semiconductor elements 222 and 221 are discovered. The removal of the layer 104 is for example realized by anisotropic etching.
    [0036] At the stage illustrated in FIG. 45, the semiconductor elements 221 and 222 are silicidized on either side of the plug 26. The silicidation typically comprises a Ni or NiPt type metal deposition, for example a annealing, then chemical removal of the unreacted metal, and generally a new annealing step. Silicone semiconductor elements 223 and 224 are thus formed on either side of the plug 226. These elements 223 and 224 may have the same composition as in the first embodiment. Advantageously, the siliciding is carried out on a thickness of 5 to 15 nm.
    [0037] In the stage illustrated in FIG. 46, a metal layer 110 has been deposited on the silicide elements 223 and 224, and on the insulation trench 32, as well as on the sides of the grooves 28, 29 and 28. 38,39 respectively 5 formed on either side of the plugs 26 and 36. The deposited metal is typically titanium. The thickness of metal deposited on the flanks of the grooves may advantageously be between 2 and 15 nm. The thickness of metal deposited on the bottom of the grooves may advantageously be between 2 and 15 nm. The metal layer 110 is advantageously deposited by a method of the CVD type, in order to have a similar thickness on the horizontal and vertical walls. Subsequently, a conductive metal alloy layer 111 was deposited on the metal layer 110. The metal alloy layer 111 typically includes TiN. The thickness of the layer 111 deposited on the flanks of the grooves may advantageously be between 3 and 10 nm. The thickness of the layer 111 deposited on the bottom of the grooves may advantageously be between 3 and 10 nm. The layer 111 is advantageously deposited by a compliant process (ALD, or CVD). Metal was then deposited on the layer 111, so as to fill the grooves by metal studs 274 and 275 on either side of the plug 26, and metal studs 374 and 375 on either side. Plug 36. The metal deposited to form the metal pads is typically Tungsten. It is also possible to consider, without limitation, aluminum, cobalt, copper, platinum or WSi.
    [0038] At the stage illustrated in FIG. 47, a chemical mechanical polishing has been carried out here and was interrupted after reaching the plugs 26 and 36. In the stage illustrated in FIG. 48, interconnecting metal contacts 273, 373, 272, 271, 372, 371 were respectively formed. with the pads 24,34, 274,275,374,375. The metal contacts 272, 271 and 273 are respectively in contact with the source, the drain and the gate of the transistor 2. In practice, the memory point 3 comprises a first memory cell between the pad 34 and the pad 374 on the one hand and another memory cell between the pads 34 and the pads 375. Although not detailed, the manufacturing method according to the second embodiment can also be used to fabricate transistors 22 and memory cells having electrodes in common , as in the example illustrated in FIG. 25. As detailed in the preceding examples, a same memory point 5 makes it possible to delimit two horizontal stacks, to form two memory cells. FIG. 49 is a partial top view of an exemplary integrated circuit 1, illustrating a memory point 3 with two cells formed on either side of a conductive pad 34, and respective selection transistors 2.
    [0039] The top view illustrated in FIG. 50 represents an integrated circuit variant 1 in which the memory point 3 comprises two memory cells on either side of the pad 34 along a first axis, and two memory cells on each side of the card. another of the stud 34 along a second axis. The memory point 3 thus comprises four memory cells. The stud 34 forms a first electrode 15 common to each of these memory cells, the pads 374 to 377 forming respective connection pads for these memory cells. Each memory cell comprises a respective selection transistor, the connections with these selection transistors being not detailed.
    [0040] Although the invention described in the preceding examples is applied to solid-type substrates, the invention also applies to silicon-on-insulator substrates, as in the example illustrated in FIG. buried insulator 120 is integrated in the substrate 100. The buried insulating layer 120 may for example be of the UTBOX type. Polarized ground planes can be arranged in a manner known per se under the UTBOX insulating layer. The integrated circuit 1 may for example be applied to make FDSOI type transistors. Whether in bulk (bulk) or SOI technology, the transistors can be planar or three-dimensional, with a finFET or triple grid geometry (for example, for trigate in the English language). Although the invention described in the preceding examples comprises semiconductor elements 221 and 222 formed with epitaxial growth, it is also conceivable to dispense with these elements 221 and 222 to protect the source and drain of transistor 2 only in the semiconductor of the substrate 100. The top view illustrated in FIG. 52 represents an integrated circuit variant 1 making it possible to further increase the integration density. Several memory points 3 comprise two cells on either side of pads 34. Several memory points comprise common pins 474. Selection transistors 2 and 4 are also connected and comprise pads 275 that are common with cells of memory cells. 3 end.
    [0041] The top view illustrated in FIG. 53 represents another variant of an integrated circuit 1 making it possible to optimize the integration density. Several memory points 3 comprise two cells on either side of pads 24. Transistors 2 and 4 are arranged on either side of each memory point 3. The pad 24 is used as a common pad for the gate of a gate. transistor 2, the gate 10 of a transistor 4, and an electrode of a memory point 3. The top view illustrated in FIG. 54 represents another variant of an integrated circuit 1 making it possible to optimize the integration density, in the particular case of FinFET transistors, i.e., three-dimensional active area transistors. The pad 24 is used as a common pad for the gates of several transistors 2, and for the electrodes of several memory cells 3.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. Method of manufacturing an integrated circuit (1) including at least one field effect transistor (2) and a memory cell (3) of the OxRam type, characterized in that it comprises the steps of: -providing a substrate ( 100) including a semiconductor layer, the substrate being provided with first and second dummy gates (21,31) and an encapsulation layer (106) in which said dummy gates (21,31) are disposed, minus the first dummy gate being formed on the semiconductor layer of the substrate; removing the first and second dummy gates to provide first and second grooves (23,33) in said encapsulation layer (106); simultaneously depositing a layer of gate insulator (107) at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode (24) of said transistor (2) in the first groove above said gate insulator layer, forming source and drain electrodes (274,275) of said transistor on either side of said gate insulator layer; said gate electrode, forming first and second electrodes of said memory cell (374,34) on either side of said gate insulator layer deposited on a side wall of the second groove.
    [0002]
    2. A method of manufacturing an integrated circuit (1) according to claim 1, comprising the formation of an insulating wall disposed between said first and second electrodes (374, 34) of the memory cell (3), said insulating wall including said gate insulator layer (107) deposited on a side wall of the second groove (33), and having a thickness dimensioned to selectively form a conductive filament upon application of a potential difference between the first and second electrodes.
    [0003]
    A method of manufacturing an integrated circuit (1) according to claim 2, further comprising forming an additional layer of insulator (108) in said second groove (33) on said gate insulator layer ( 107), said additional layer of insulator being included in said insulating wall disposed between said first and second electrodes (374,34).
    [0004]
    A method of manufacturing an integrated circuit (1) according to any one of the preceding claims, wherein said deposited gate insulator layer (107) includes a material selected from the group consisting of HfO2, HfSiON, HfA10, TiOx, A1203 or NiO. 3034906 25
    [0005]
    A method of manufacturing an integrated circuit (1) according to any one of the preceding claims, wherein forming the source, drain and said first electrode of the memory cell includes forming additional grooves (28). , 29, 38) in the encapsulation layer (106), on either side of the first groove (23) and on the side of the second groove (33).
    [0006]
    The method of manufacturing an integrated circuit according to claim 5, comprising depositing a protective layer (26,36) in the first and second grooves respectively on said gate electrode (24) and said second electrode ( 34) of the memory cell, said protective layer being formed in a material different from the encapsulation layer, the formation of said additional grooves including self-aligned etching of the encapsulation layer (106) on either side of the encapsulation layer. the protective layer (26,36).
    [0007]
    A method of manufacturing an integrated circuit according to claim 5 or 6, wherein forming the source, drain and said first electrode of the memory cell includes: forming a titanium layer ( 110) on the walls of said additional grooves; forming a layer of titanium nitride (111) on the titanium layer; depositing a metal layer on said titanium layer. 25
    [0008]
    The manufacturing method according to any one of the preceding claims, wherein said first electrode formed for said memory cell (3) also forms one of said source or drain electrodes formed for said transistor (2). 30
    [0009]
    The manufacturing method according to any one of the preceding claims, wherein said provided substrate (100) comprises an isolation trench (32) and wherein the second dummy gate (31) is formed on said isolation trench. 35
    [0010]
    10. The manufacturing method according to any one of the preceding claims, wherein said substrate (100) is of silicon-on-insulator type.
    [0011]
    The manufacturing method as claimed in any one of the preceding claims, comprising connecting said first and second electrodes (374, 375) of said memory cell (3) to an electronic circuit configured to selectively apply a potential difference between the first and second electrodes (374, 375). and second electrodes inducing a conductive filament through said gate insulator layer (107) deposited on a side wall of the second groove.
    [0012]
    12. The manufacturing method according to any one of the preceding claims, comprising: forming said encapsulation layer (106); prior to the formation of said encapsulation layer, a full-plate deposit of an insulating layer (104) covering the first and second dummy grids; Masking said insulating layer (104) at the first dummy gate (21) and removing said insulating layer (104) above and on either side of the second dummy gate (31); -containing a portion of said insulating layer (104) on either side of said formed gate electrode (24) so as to form spacers for said gate electrode (24).
    [0013]
    The manufacturing method according to claims 5 and 12, wherein said masking and said shrinkage are performed prior to said formation of said encapsulation layer (106). 20
    [0014]
    14. The manufacturing method according to claims 5 and 12, wherein said masking and said withdrawal are made subsequent to the formation of said additional grooves (28,29,38). 25
    [0015]
    Integrated circuit (1) including: a field effect transistor (2); a memory cell (3) of the OxRAM type; characterized in that: the field effect transistor (2) and the memory cell (3) are included in a pre-metallization layer and in which a gate insulator layer of the field effect transistor (2 ) and an insulation layer selectively forming a conductive filament of the memory cell (3) include the same material.
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    同族专利:
    公开号 | 公开日
    US9711567B2|2017-07-18|
    US20160300884A1|2016-10-13|
    EP3079178B1|2018-01-17|
    FR3034906B1|2018-06-22|
    EP3079178A1|2016-10-12|
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    法律状态:
    2016-04-28| PLFP| Fee payment|Year of fee payment: 2 |
    2016-10-14| PLSC| Search report ready|Effective date: 20161014 |
    2017-04-28| PLFP| Fee payment|Year of fee payment: 3 |
    2018-04-26| PLFP| Fee payment|Year of fee payment: 4 |
    2020-02-14| ST| Notification of lapse|Effective date: 20200108 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1553070A|FR3034906B1|2015-04-09|2015-04-09|METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COINTEGRATING A FET TRANSISTOR AND A MEMORY POINT OXRAM|
    FR1553070|2015-04-09|FR1553070A| FR3034906B1|2015-04-09|2015-04-09|METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT COINTEGRATING A FET TRANSISTOR AND A MEMORY POINT OXRAM|
    EP16163744.2A| EP3079178B1|2015-04-09|2016-04-04|Method for manufacturing an integrated circuit co-integrating a fet transistor and an oxram memory point|
    US15/094,011| US9711567B2|2015-04-09|2016-04-08|Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location|
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